Title :
0.5 μm 1 M gate CMOS SOG
Author :
Ikeda, Nobuyuki ; Ishibashi, Atsuhiko ; Maeno, Hideshi ; Matsue, Shuichi ; Asahina, Katsushi ; Arakawa, Takahiko ; Kato, Shuichi
Author_Institution :
Mitsubishi Electric Corp., Hyogo, Japan
Abstract :
A one-million-gate CMOS SOG (sea-of-gates) array has been developed by using half-micron three-layer metal CMOS technology. The high speed I/O (input/output) buffers, RAM cell libraries, and clock skew management make it possible to achieve over 100 MHz operating at 3.3 V. A gate density of 4.7 kG/mm2 and a bit density of 1.8 kbit/mm2 for asynchronous dual-port RAMs are obtained. The GTL (Gunning transceiver logic) interface cells are prepared in the I/O buffer cell library. The clock skew is less than 500 ps under 5000 flip-flops at 100 MHz on the chip
Keywords :
CMOS logic circuits; 0.5 micron; 100 MHz; 3.3 V; ASIC; GTL interface cells; Gunning transceiver logic; RAM cell libraries; analog PLL; asynchronous dual-port RAMs; clock skew management; flip-flops; high speed I/O; low voltage; macrocell; one-million-gate CMOS SOG; sea-of-gates array; three-layer metal CMOS technology; Application specific integrated circuits; CMOS technology; Clocks; Design engineering; Energy consumption; Flip-flops; Libraries; Power dissipation; Power supplies; Read-write memory;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590755
