A 30-ps jitter, 3.6-μs locking, 3.3-volt digital PLL for CMOS gate arrays

A 3.3-V digital phase-locked loop (DPLL) with a 30-ps jitter resolution and 3.6-μs locking time has been developed to support a 0.65-μm CMOS gate array. The innovative DPLL features dual-mode automatic control logic for coarse and fine locking, and autorecovery circuitry to compensate for locking failure due to substantial system clock drift, and a nominal 200-μW power dissipation. Multiple DPLLs can be utilized in each gate array to support system clocks of above 100 MHz. Low-power operation is accomplished with no DC-current-consuming circuitry, in order to better serve portable applications. Multiple high-resolution DPLL instances are allowed on virtually any spot of the die, and support either 3.3-V or 5-V operation. System reliability is enhanced by the implementation of the autorecovery circuitry which monitors the high-resolution DPLL for faults caused by poor system and environmental control