Title :
Interface techniques for embedding custom mega cells in a gate array
Author :
Ashby, Laurin R.
Author_Institution :
Motorola Inc., Chandler, AZ, USA
Abstract :
A full custom microprocessor mega cell is embedded in a 0.7-micron triple-layer metal gate array using shrinkable design rules. Interface logic built from gate array macros guarantees data sheet timing at the pins, production test pattern transportability, and CRC/BIST (cyclic redundancy check/built-in self-test) testability. The processor was modeled using behavioral Verilog wrapped around proprietary `C´ code
Keywords :
microprocessor chips; 0.7 micron; ASIC; BIST testability; C model; behavioral Verilog; cyclic redundancy check testability; data sheet timing; embedding; full custom; gate array macros; interface logic; microprocessor mega cell; production test pattern transportability; shrinkable design rules; simulation; timing verification; triple-layer metal gate array; Automatic testing; Built-in self-test; Cyclic redundancy check; Logic arrays; Logic gates; Logic testing; Microprocessors; Pins; Production; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590758
