Design and optimization of high-voltage CMOS devices compatible with a standard 5 V CMOS technology

Author

Declercq, M. ; Clement, F. ; Schubert, M. ; Harb, A. ; Dutoit, M.

Author_Institution

Swiss Federal Inst. of Technol., Lausanne, Switzerland

fYear

1993

fDate

9-12 May 1993

Abstract

High-voltage n- and p-MOSFETs fully compatible with a standard 5 V CMOS technology have been designed, optimized, and fabricated. No process changes are required. By modifying the logical equations generating one of the physical masks from the design masks, a p-type buffer region for the high-voltage p-MOS was easily implemented. This modification does not affect the low-voltage part of the circuits. These high-voltage devices have been used successfully as output drivers in semicustom arrays, and as building blocks for custom low- to high-voltage output interfaces. Aspects of reliability, device protection, and circuit design techniques are addressed

Keywords

power integrated circuits; 5 V; 75 V; circuit design techniques; custom interfaces; design masks; device protection; high-voltage CMOS devices; n-MOSFET; optimization; output drivers; p-MOSFET; p-type buffer region; physical masks; reliability; semicustom arrays; smart power circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; CMOS technology; Design optimization; Implants; Laboratories; MOSFETs; Power system reliability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590766

Filename

590766