11th IEEE International On-Line Testing Symposium

fYear

2005

fDate

6-8 July 2005

Abstract

The following topics are dealt with: transient fault modeling and analysis; transient faults´ hardening techniques; SEU effects in FPGA; soft errors; single-event effects; self-calibrating design; online testing for secure and asynchronous chips; self-checking strategies; process variations; leakage detection; power supply noise detection; integrated circuit testing; SoC testing; fault tolerance; multiple bit upset evaluation and correction; integrated circuit yield; and integrated circuit reliability.

Keywords

asynchronous circuits; built-in self test; fault tolerance; field programmable gate arrays; integrated circuit design; integrated circuit reliability; integrated circuit testing; integrated circuit yield; system-on-chip; SEU effects; SoC testing; asynchronous chips; fault tolerance; field programmable gate arrays; integrated circuit reliability; integrated circuit testing; integrated circuit yield; leakage detection; multiple bit upset correction; multiple bit upset evaluation; online testing; power supply noise detection; process variations; secure chips; self-calibrating design; self-checking strategies; single-event effects; soft errors; transient fault modeling; transient faults hardening;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International

Conference_Location

French Riviera

Print_ISBN

0-7695-2406-0

Type

conf

DOI

10.1109/IOLTS.2005.4

Filename

1498114