Title :
A high performance/low power 16 K-byte 4-way set associative integrated cache macro
Author :
Nguyen, Kim Y. ; Flaker, Roy ; Roberts, AI ; Holman, T. ; Benson, Reg ; Lavalette, Dave ; Robillard, Marcel ; Nietupski, Dan ; Davis, Andrew
Author_Institution :
IBM East Fishkill, Hopewell Junction, NY, USA
Abstract :
The high-performance, low-power 16 K-byte 4-way set associative integrated cache memory currently being used in the IBM 486 SLC/486 SLC2 microprocessor chips is described. The integrated cache combines the functions of the 20 K bit TAG memory, 1 K bit STATE, 2 K bit LRU (least recently used), and 144 K bit DATA memory. This is key to reducing interface complexity and optimizing size, power, and performance. The integrated cache unit has a typical clock to DATA access of 6.9 ns and clock to HIT access of 5.0 ns in a 12 ns cycle time. It has a worst-case power of 400 mW at 50% utilization. The integrated cache was designed and built in 0.8 μm CMOS technology. It features novel circuit design techniques such as high-performance dynamic comparators in TAG and LRU arrays, self-timed restore, read-modified-write on all arrays in one cycle, and very fast flush/reset in STATE array
Keywords :
CMOS memory circuits; 0.8 micron; 16 Kbyte; 4-way set associative; 400 mW; CMOS technology; STATE array; TAG memory; architecture; dynamic comparators; high-performance; integrated cache macro; interface complexity; least recently used; low-power; microprocessor chips; read-modified-write; self-timed restore; timing simulation; worst-case power; CMOS technology; Cache memory; Clocks; Decoding; Logic arrays; Logic devices; Power system restoration; Read-write memory; Signal generators; Technical Activities Guide -TAG;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590769
