• DocumentCode
    1817384
  • Title

    An efficient architecture for two-dimensional inverse discrete wavelet transform

  • Author

    Wu, Po-Cheng ; Huang, Chao-Tsung ; Chen, Liang-Gee

  • Author_Institution
    Network Commun. Lab., Inst. for Inf. Ind., Taipei, Taiwan
  • Volume
    2
  • fYear
    2002
  • fDate
    2002
  • Abstract
    This paper proposes an efficient architecture for the two-dimensional inverse discrete wavelet transform (2D IDWT). The proposed architecture includes an inverse transform module, a RAM module, and a multiplexer. In the inverse transform module, we employ the coefficient folding technique and the polyphase decomposition technique to the interpolation filters of stages 1 and 2, respectively. The RAM size is N/2×N/2. The advantages of the proposed architecture are the 100% hardware utilization, fast computing time, regular data flow, and low control complexity, making this architecture suitable for next generation image coding/decoding systems.
  • Keywords
    circuit complexity; discrete wavelet transforms; image processing equipment; interpolation; microprocessor chips; multiplexing equipment; random-access storage; 2D IDWT; 2D inverse discrete wavelet transform architecture; RAM module; RAM size; VLSI design technologies; coefficient folding technique; computing time; control complexity; hardware utilization; image coding/decoding systems; interpolation filters; inverse transform module; multiplexer; polyphase decomposition technique; processors; regular data flow; Computer architecture; Control systems; Data flow computing; Discrete transforms; Discrete wavelet transforms; Filters; Hardware; Image coding; Interpolation; Multiplexing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
  • Conference_Location
    Phoenix-Scottsdale, AZ
  • Print_ISBN
    0-7803-7448-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2002.1010987
  • Filename
    1010987