• DocumentCode
    1817550
  • Title

    FUNTASSI: A functional test generation assistant

  • Author

    Kohno, Kazuyoshi ; Sekine, Masatoshi

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • fYear
    1993
  • fDate
    9-12 May 1993
  • Abstract
    A tool for generating stimuli for functional verification from a register transfer level description with a `path activation´ technique is described. A novel test generation tool for checking functional behaviors at the register transfer level is presented. Experiments have shown that stimuli generated for functional verification at the register transfer level are acceptable for practical designs. The stimuli generated by FUNTASSI can be used for functional tests at logic level design. A new design approach for checking circuit models also been addressed. That is, if FUNTASSI can generate stimuli for desired behavior under some constraints, then the design is correct
  • Keywords
    automatic test software; ATPG; DFT; FUNTASSI; HDL; circuit models; floating point arithmetic circuit; functional test generation assistant; functional verification; logic level design; node activation; path activation; path activation technique; register transfer level description; Automatic logic units; Circuit simulation; Circuit testing; Hardware design languages; Integrated circuit testing; Logic circuits; Logic design; Logic testing; Registers; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0826-3
  • Type

    conf

  • DOI
    10.1109/CICC.1993.590780
  • Filename
    590780