Title :
Impact of soft error challenge on SoC design
Author :
Zorian, Y. ; Vardanian, V.A. ; Aleksanyan, K. ; Amirkhanyan, K.
Author_Institution :
Virage Logic Corp., Fremont, CA, USA
Abstract :
Soft errors are a major challenge to robust design. Conventionally, designs with high level requirements for reliability and availability required protection against soft errors. However, the scaling level reached with today´s nanometer technologies is moving the soft error protection requirements to SoC designs for a wide range of applications. This paper discusses the soft error challenge, its implication on SoC design practices and possible approaches to create a robust SoC design.
Keywords :
integrated circuit design; nanotechnology; radiation effects; system-on-chip; SoC design; nanometer technologies; scaling level; soft error protection requirements; system-on-chip; CMOS logic circuits; CMOS process; CMOS technology; Combinational circuits; Integrated circuit technology; Latches; Protection; Robustness; Sequential circuits; Single event upset;
Conference_Titel :
On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
Print_ISBN :
0-7695-2406-0
DOI :
10.1109/IOLTS.2005.36
