Title :
Metastability behavior of mismatched CMOS flip-flops using state diagram analysis
Author :
Noije, W. A M Van ; Liu, W.T. ; Navarro, S., Jr.
Author_Institution :
Sao Paulo Univ., Brazil
Abstract :
The effect on the metastability of the mismatch of FET parameters and load capacitances in a CMOS latch/flip-flop is analyzed. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semiplanes, which precisely determine the latch final state. SPICE simulation results are shown for matched/mismatched flip-flops
Keywords :
flip-flops; FET parameters; SPICE simulation; latch final state; load capacitances; metastability; mismatched CMOS flip-flops; semiplanes; state diagram analysis; transient analysis; Capacitance; Circuit simulation; Clocks; FETs; Flip-flops; Inverters; Latches; Metastasis; Very large scale integration; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590809
