DocumentCode
1817902
Title
A high resolution sigma-delta modulator with extended dynamic range
Author
Williams, Louis A., III ; Wooley, Bruce A.
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
fYear
1993
fDate
9-12 May 1993
Abstract
The authors introduce a third-order cascaded sigma-delta modulator that uses a modified cascaded architecture and reduced gain in the first integrator to increase the dynamic range. An experimental modulator fabricated in a 1-μm CMOS technology attains 17-bit performance for a 25-kHz signal bandwidth using a single 5-V supply. With an oversampling ratio of 128 and a clock frequency of 6.4 MHz, the modulator achieves a 104-dB dynamic range and a peak signal-to-noise plus distortion ratio (SNDR) of 98 dB
Keywords
sigma-delta modulation; 1 micron; 25 kHz; 5 V; 6.4 MHz; CMOS technology; extended dynamic range; high resolution sigma-delta modulator; modified cascaded architecture; reduced gain; third-order cascaded; Analog-digital conversion; Analytical models; Circuit noise; Delta-sigma modulation; Dynamic range; Integrated circuit noise; Noise reduction; Noise shaping; Quantization; Semiconductor device noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0826-3
Type
conf
DOI
10.1109/CICC.1993.590814
Filename
590814
Link To Document