Use of a 90° phase shift detector and sampled-data loop filter in PLL

A modified architecture of a PLL that permits a fully monolithic integration is proposed. The key features of the architecture are the use of a phase frequency detector (PFD) operating on a 90° phase shift and a switched capacitor filter instead of a passive filter. The PFD operates with relatively long current pulses, thus reducing non-ideality with respect to the conventional PFD. A behavioral model in Matlab-Simulink has been used for different PFDs and low pass filters (LPF) used in the proposed architecture. Results show that the proposed solution achieves the same performances as a conventional solution with 11 times less capacitance.