Title :
Multilevel optimization of high speed VLSI interconnects using decomposition
Author :
Wei, Y. ; Zhang, Q.J. ; Nakhla, M.S.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
A multilevel optimization technique is developed for large-scale and hierarchical optimization of high-speed VLSI interconnects modeled by distributed transmission lines. Mathematical programming decomposition is combined with network tearing where the overall network is optimized by a set of parallel suboptimizations. The technique takes advantage of VLSI interconnects in the hierarchy of IC, MCM (multichip module), and PCB (printed circuit board), and is much faster than standard optimization
Keywords :
very high speed integrated circuits; distributed transmission lines; frequency-domain; hierarchical optimization; high speed VLSI interconnects; mathematical programming decomposition; multilevel optimization; network tearing; parallel suboptimizations; time-domain; Coupling circuits; Crosstalk; Design optimization; Integrated circuit interconnections; Large-scale systems; Limiting; Mathematical programming; Very large scale integration; Virtual colonoscopy; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590820
