DocumentCode
1818130
Title
Fast, parallel two-rail code checker with enhanced testability
Author
Matakias, S. ; Arapoyanni, A. ; Efthymiou, A. ; Tsiatouhas, Y. ; Haniotakis, Th
Author_Institution
Dept. of Informatics & Telecom., Athens Univ., Greece
fYear
2005
fDate
6-8 July 2005
Firstpage
149
Lastpage
156
Abstract
A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for high n-variable (high fan-in) implementations, is presented. The checker is characterized by high testability, high operating frequencies and low silicon area requirements. The circuit has been designed, for various n-variable values, in a 0.18μm technology and SPICE simulations have been carried out to validate its operation.
Keywords
SPICE; design for testability; error detection codes; integrated circuit design; 0.18 micron; SPICE simulations; enhanced testability; high fan-in implementations; high n-variable implementation; operating frequencies; silicon area requirements; two-rail code checker; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Circuit topology; Frequency; Informatics; Monitoring; Silicon; Telecommunications;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
Print_ISBN
0-7695-2406-0
Type
conf
DOI
10.1109/IOLTS.2005.29
Filename
1498149
Link To Document