Title :
Reliability assessment of self-timed VLSI circuits
Author :
Chang, Chen Hao ; Sheu, Bing J. ; Gowda, Sudhir M.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Self-timed VLSI circuits can avoid problems of clock distribution and achieve 500 MHz or higher-speed data processing. The RELY circuit reliability simulator is used to investigate the comparative reliability of two-phase, single-phase, and self-timed circuits. Reliability simulation techniques and analysis results on submicron CMOS circuits are presented
Keywords :
CMOS logic circuits; RELY circuit reliability simulator; asynchronous circuits; clocked circuits; comparative reliability; hot carrier degradation; latches; self-timed VLSI circuits; submicron CMOS circuits; Analytical models; CMOS technology; Circuit simulation; Clocks; Degradation; Integrated circuit reliability; MOSFETs; Monitoring; Substrates; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590825
