Title :
A pragmatic approach to concurrent error detection in sequential circuits implemented using FPGAs with embedded memory
Author :
Krasniewski, Andrzej
Author_Institution :
Inst. of Telecommun., Warsaw Univ. of Technol., Poland
Abstract :
We present several low-cost concurrent error detection schemes for a sequential circuit implemented using FPGAs with embedded memory blocks. The experimental results show that for many of the examined circuits, a reasonable level of error detection can be obtained at the circuitry overhead of less than 10% - a level recommended by proponents of a "pragmatic" approach to on-line testing.
Keywords :
SRAM chips; embedded systems; error detection; field programmable gate arrays; sequential circuits; FPGA; embedded memory; error detection; on-line testing; pragmatic approach; sequential circuits; Circuit faults; Circuit testing; Circuits and systems; Clocks; Costs; Electrical fault detection; Fault detection; Field programmable gate arrays; Registers; Sequential circuits;
Conference_Titel :
On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
Print_ISBN :
0-7695-2406-0
DOI :
10.1109/IOLTS.2005.11
