A pragmatic approach to concurrent error detection in sequential circuits implemented using FPGAs with embedded memory

Author

Krasniewski, Andrzej

Author_Institution

Inst. of Telecommun., Warsaw Univ. of Technol., Poland

fYear

2005

fDate

6-8 July 2005

Firstpage

197

Lastpage

198

Abstract

We present several low-cost concurrent error detection schemes for a sequential circuit implemented using FPGAs with embedded memory blocks. The experimental results show that for many of the examined circuits, a reasonable level of error detection can be obtained at the circuitry overhead of less than 10% - a level recommended by proponents of a "pragmatic" approach to on-line testing.

Keywords

SRAM chips; embedded systems; error detection; field programmable gate arrays; sequential circuits; FPGA; embedded memory; error detection; on-line testing; pragmatic approach; sequential circuits; Circuit faults; Circuit testing; Circuits and systems; Clocks; Costs; Electrical fault detection; Fault detection; Field programmable gate arrays; Registers; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International

Print_ISBN

0-7695-2406-0

Type

conf

DOI

10.1109/IOLTS.2005.11

Filename

1498157

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1818285