Accumulator-based weighted pattern generation

Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in built in self test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 have been successfully utilized within the weighted pattern generation paradigm. In this paper an accumulator-based scheme is presented, that generates set of patterns with weights 0, 0.5 and 1. Since accumulators and ALUs are commonly found in current VLSI chips, the presented scheme can be efficiently utilized to drive down the hardware of BIST pattern generation.