Integrating BIST techniques for on-line SoC testing

Today´s complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly designed for test, are coupled with functional IPs both to obtain yield improvement during the manufacturing process and to perform volume production test. In some fields (e.g., the automotive one) there is a strong need for flexible and reusable test architectures able to guarantee effective and low-cost solutions for mission-mode fault detection capabilities within complex SoCs. In this paper, we propose to reuse structures inserted to support the manufacturing test to perform non-concurrent on-line test of SoCs. The feasibility of this approach and its costs have been evaluated on a real case of study including processor, memory and user defined logic cores.