Increasing fault tolerance to multiple upsets using digital sigma-delta modulators

As the transistor gate length goes straightforward to the sub-micron dimension, there is an increased possibility of occurrence of external interferences in these devices. The direct effect of such external and/or intrinsic interferences is, in many cases, the total mismatch between the desired answer of the system and the obtained response. So, new techniques must be studied in order to guarantee the correct operation of these systems, under multiple simultaneous faults. This work presents the use of a totally digital sigma-delta modulator that is used to develop arithmetic operations with much better results than if a common digital operator was used. Simulation results show that, even under multiple simultaneous faults, the system presents very good results, as in the addition case, where a maximum standard deviation of 0.7 is achieved for sigma-delta-modulated signals, while for the digital adder alone, this value is 57.5. Such behavior is good enough to be used in operators that tolerate small errors, like in the digital filters where these errors are embedded in the system noise.