Title :
How to cope with SEU/SET at chip level? The example of a microprocessor family
Author_Institution :
ATMEL, Nantes, France
Abstract :
The concern related to heavy tons or protons single event induced effects has grown with the transistor size reduction. With the example of a microprocessor family for the space market, this paper focuses on the evolution of the methods used to mitigate against single event upsets (SEU) and transients (SET) on these products.
Keywords :
CMOS integrated circuits; microprocessor chips; radiation effects; radiation protection; SET; SEU; chip level; microprocessor; CMOS process; CMOS technology; Digital signal processing; Flip-flops; Manufacturing; Microprocessors; Protection; Radiation hardening; Single event upset; Space technology;
Conference_Titel :
On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
Print_ISBN :
0-7695-2406-0
DOI :
10.1109/IOLTS.2005.33
