Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory

Author

Lee, Kung-Hong ; Wang, Shih-Chen ; King, Ya-Chin

Author_Institution

Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan

fYear

2005

fDate

5-5 Aug. 2005

Firstpage

3

Lastpage

8

Abstract

A novel multilevel/analog electrically erasable programmable read only memory (EEPROM) cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme is proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE sub-circuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications.

Keywords

CMOS memory circuits; EPROM; SPICE; hot carriers; logic design; SPICE; complementary metal oxide semiconductor; current induced drain avalanche hot hole; hot electron erasing; logic process based multilevel/analog EEPROM memory; memory programming; nonvolatile memory; select gate controlled channel; self convergent scheme; CMOS logic circuits; CMOS process; Charge carrier processes; Circuit simulation; EPROM; Hot carriers; Logic programming; Nonvolatile memory; SPICE; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on

Conference_Location

Taipei

ISSN

1087-4852

Print_ISBN

0-7695-2313-7

Type

conf

DOI

10.1109/MTDT.2005.29

Filename

1498194