3D stacked high density packages with bumpless interconnect technology

Novel 3D stacked high-density packages fabricated with bumpless interconnect technology are presented. The single stacking unit can contain bare chips, packaged devices or passive components. A combination of compliant terminals and through-package terminals in an array under and around the chips are used as z-axis interconnects between the stacking units. To keep each single stacking unit thin, bumpless interconnect methods such as electro-chemical plating (ECP) or ball bonding are applied to connect circuit traces to the die pads directly. No wire-bonding, lead-bond, solder bumps, substrates or vacuum sputtering films are involved. The circuit traces route power and data signals to and from the chip pads to the z-axis interconnects (e.g. through-package or compliant terminals) which are orthogonal to the trace for 3D stacking and printed circuit board assembly. Single stacking units are positioned in a vertical stack with their terminals aligned to one another. A single reflow operation simultaneously bonds all unit assemblies together to form the 3D stacked high-density package. The compliant and deformable nature of solder paste and the routing traces provide flexible vertical interconnections that accommodate chips and packages with a wide range of thicknesses and sizes. The traces, compliant and through-package terminals serve as the interconnect matrix between the chips and packages, which may be functionally, similar or different from one another, thereby increasing packaging density and functionality. Details of the package design concepts, processing steps and the underlying bumpless interconnect technology are discussed along with key, advantages and applications of these novel 3D stacked high-density packages.