• DocumentCode
    1819182
  • Title

    A novel CMOS compatible embedded nonvolatile memory with zero process adder

  • Author

    Breitwisch, Matthew J. ; Lam, Chung H. ; Johnson, Jeffrey B. ; Mittl, Steven W. ; Zhu, Jian W.

  • Author_Institution
    IBM Res. Div., Yorktown Heights, NY, USA
  • fYear
    2005
  • fDate
    5-5 Aug. 2005
  • Firstpage
    9
  • Lastpage
    12
  • Abstract
    We demonstrate a CMOS compatible reprogrammable nonvolatile memory cell using a regular n-channel MOSFET with under-lapped source/drain diffusions that requires no extra processing steps in a standard 130nm CMOS logic technology. Experimental results indicate good endurance and retention characteristics. A strategy for optimizing programming efficiency is identified with the addition of one extra mask to introduce drain optimization implants.
  • Keywords
    CMOS logic circuits; MOSFET circuits; adders; random-access storage; 130 nm; CMOS logic technology; MOSFET; drain optimization; endurance characteristics; reprogrammable nonvolatile memory cell; retention characteristics; under-lapped source/drain diffusions; zero process adder; CMOS logic circuits; CMOS process; CMOS technology; Conferences; Implants; MOSFET circuits; Microelectronics; Nonvolatile memory; Space technology; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
  • Conference_Location
    Taipei
  • ISSN
    1087-4852
  • Print_ISBN
    0-7695-2313-7
  • Type

    conf

  • DOI
    10.1109/MTDT.2005.12
  • Filename
    1498195
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1819182