A built-in quiescent current monitor for CMOS VLSI circuits

Author

Rubio, A. ; Janssens, E. ; Casier, H. ; Figueras, J. ; Mateo, D. ; De Pauw, P. ; Segura, J.

Author_Institution

Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain

fYear

1995

fDate

6-9 Mar 1995

Firstpage

581

Lastpage

585

Abstract

A built-in I_DDQ monitor for CMOS digital circuits with low power supply voltage perturbation is presented. It minimizes the extra delay of the CUT in normal operation. An automatic recovery mechanism limits the drop in VDD voltage during the testing phase so the data storage is not perturbed. The I_DDQ current level may be measured by a standard digital IC tester. The performance parameters are compared with other published circuits and experimental results of an ASIC with the proposed BIC monitor are discussed

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; built-in self test; electric current measurement; integrated circuit testing; ASIC; BIC monitor; CMOS VLSI circuits; I_DDQ current level; automatic recovery mechanism; built-in quiescent current monitor; digital IC tester; power supply voltage perturbation; Automatic testing; CMOS digital integrated circuits; Circuit testing; Delay; Digital circuits; Low voltage; Memory; Monitoring; Power supplies; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1995. ED&TC 1995, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-7039-8

Type

conf

DOI

10.1109/EDTC.1995.470341

Filename

470341