A programmable built-in self-test for embedded DRAMs

Author

Banerjee, Shibaji ; Chowdhury, Dipanwita Roy ; Bhattacharya, Bhargab B.

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

fYear

2005

fDate

5-5 Aug. 2005

Firstpage

58

Lastpage

63

Abstract

A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a built-in self-test (BIST) architecture is proposed with low area overhead. The test pattern generator (TPG) for generating all patterns for NPSFs is implemented with on-chip cellular automata (CA) based circuit.

Keywords

DRAM chips; automatic test pattern generation; built-in self test; embedded systems; fault simulation; logic testing; active neighborhood pattern sensitive faults; address decoder faults; cellular automata-based circuit; coupling faults; embedded DRAM; memory test algorithm; passive neighborhood pattern sensitive faults; programmable built-in self-test; static neighborhood pattern sensitive faults; stuck-at faults; test pattern generator; transition faults; Built-in self-test; Clocks; Conferences; Content addressable storage; Decoding; Pins; Random access memory; Signal design; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on

Conference_Location

Taipei

ISSN

1087-4852

Print_ISBN

0-7695-2313-7

Type

conf

DOI

10.1109/MTDT.2005.14

Filename

1498204