DocumentCode
1819494
Title
DFT architecture for a dynamic fault model of the embedded mask ROM of SOC
Author
Lee, Yang-Han ; Jan, Yih-Guang ; Shen, Jei-Jung ; Tzeng, Shian-Wei ; Chuang, Ming-Hsueh ; Lin, Jheng-Yao
Author_Institution
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
fYear
2005
fDate
5-5 Aug. 2005
Firstpage
78
Lastpage
82
Abstract
This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC "of passing in the high speed test, but fails in the low speed test", and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time.
Keywords
design for testability; fault simulation; logic gates; logic testing; production testing; read-only storage; system-on-chip; DFT architecture; NAND-type mask ROM; design for testability; dynamic fault model; embedded mask ROM; mass product testing; read-only memory; system-on-chip; Batteries; Decoding; Electronic mail; Frequency; Random access memory; Read only memory; Resistors; System-on-a-chip; Testing; Variable structure systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
Conference_Location
Taipei
ISSN
1087-4852
Print_ISBN
0-7695-2313-7
Type
conf
DOI
10.1109/MTDT.2005.8
Filename
1498207
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