DocumentCode :
1819577
Title :
A systematic approach to reducing semiconductor memory test time in mass production
Author :
Yeh, Jen-Chieh ; Kuo, Shyr-Fen ; Wu, Cheng-Wen ; Huang, Chih-Tsun ; Chen, Chao-Hsun
Author_Institution :
Dept. of Electr. Eng., National Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2005
fDate :
5-5 Aug. 2005
Firstpage :
97
Lastpage :
102
Abstract :
Semiconductor memory testing has been a key problem in testing integrated circuits for years. With their growing density and capacity, the test time grows rapidly if the test methodologies and equipments remain the same. Test time reduction other than parallel insertion - which is expensive and more and more difficult to keep up with the memory capacity growth - is a long time research issue, as test cost is directly related to the time each product stays on the tester. In order to solve the test time reduction (TTR) problem, we propose a systematic approach to analyzing and rearranging the test items in the test flow. We propose three test compaction techniques: 1) removing redundant test items, 2) merging existing test patterns, 3) developing efficient new test patterns. The proposed TTR algorithm is shown to effectively reduce the test time of an industrial DRAM product. The TTR tool also can identify the redundant test items, suggest a proper test list, and provide the correlation between the test items. In the industrial case, about 19.5% of the total test time is reduced, on top of the original manually compacted test flow.
Keywords :
DRAM chips; automatic test pattern generation; integrated circuit testing; mass production; production testing; DRAM product; integrated circuits testing; mass production test; memory capacity growth; parallel insertion; redundant test items; semiconductor memory testing; test compaction; test patterns; test time reduction; Circuit testing; Compaction; Costs; Integrated circuit testing; Mass production; Merging; Random access memory; Semiconductor device testing; Semiconductor memory; System testing; RAM; mass production test; memory testing; semiconductor memory; test time reduction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
Conference_Location :
Taipei
ISSN :
1087-4852
Print_ISBN :
0-7695-2313-7
Type :
conf
DOI :
10.1109/MTDT.2005.15
Filename :
1498210
Link To Document :
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