Reducing buffer requirement for VC-merge capable ATM switches

Author

Zhou, Peifang ; Yang, Oliver W W

Author_Institution

Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont., Canada

fYear

1999

fDate

1999

Firstpage

44

Abstract

The multiprotocol label switching (MPLS) paradigm of integrating layer-3 routing with layer-2 switching has been proposed as a viable alternative to today´s router architecture. When MPLS is applied to the design of large core routers, label merging is required in order to support scalability. In this paper, we assume that ATM is the layer-2 switching mechanism. We investigate the impact of VC merging on buffer requirement. Results indicate that buffer requirement of VC merging can be excessive when compared to non-VC merging. This is in contrast to previous findings. We propose three schemes to significantly reduce the buffer requirement for VC merging

Keywords

asynchronous transfer mode; buffer storage; packet switching; protocols; telecommunication network routing; AAL5; ATM switches; IP packet encapsulation method; MPLS paradigm; VC merging; buffer requirement reduction; error detection; label merging; large core router design; layer-2 switching; layer-3 routing; nonVC merging; random early detection; router architecture; scalability; Asynchronous transfer mode; Electronic mail; Information technology; Internet; Merging; Multiprotocol label switching; Routing; Scalability; Switches; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1999. GLOBECOM '99

Conference_Location

Rio de Janeireo

Print_ISBN

0-7803-5796-5

Type

conf

DOI

10.1109/GLOCOM.1999.831605

Filename

831605