Impact of stresses on the fault coverage of memory tests

Memory tests are applied in the industry using different algorithmic stresses (e.g., data-backgrounds) and non-algorithmic stresses (e.g., supply voltage). This paper presents an industrial analysis of the impact of stresses on the fault coverage (FC) of the memory tests. The experimental results show that stresses have an important impact on the FC, that the variation of the FC due to non-algorithmic stresses is higher than that of algorithm stresses, and that the non-algorithmic stresses achieve a better FC than algorithm stresses. The paper also discusses the causes behind this variation in the FC and concludes that the variation can be barely explained with the current fault models, and that this increasing variation is potentially due to partially/not modeled/understood defect mechanism in the scaled memory technologies (e.g., increase in voltage drop, in cross talk and in leakage; reduction in noise margin, etc).