The design and fabrication of a 50KVA 450A silicon carbide power electronic module

The design and packaging issues associated with a 50KVA 450A power electronic module using parallel configuration of 1200V, 50A silicon carbide (SiC) MOSFETs and diodes are presented. The module was designed to fit into an existing package housing with an inside substrate surface area of 96mm×32mm on a direct bond copper (DBC) substrate. The main contributors of the parasitic inductances are the gate loop inductance, switching loop inductance, and the common source inductance. These stray inductances severely affect the switching performance of the power module. As such, parasitic inductances were minimized by using multiple large diameter bond wires with their length as short as possible. The copper conduction paths should be wide and short. The parasitic extraction shows that the inductances vary from 10nH to 76nH. The conduction losses, about 186W and 178W for the high and low sides, respectively, are extracted from simulation taking into consideration the copper conduction path resistances and the desired current rating of the power module. Conduction losses are reduced by using larger diameter bond wires for the electrical connection between the devices and the connection pads. The conduction loss is approximately 270W for both high and low side switching positions when 0.15mm diameter bond wires are used to connect the devices to the connection pads compared to 186W and 178W for high and low side switching positions when 0.38mm diameter bond wires are used.