Title :
Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis
Author :
Natsui, Masanori ; Aoki, Takafumi ; Higuchi, Tatsuo
Author_Institution :
Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
This paper presents an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and its extension to a parallel version. The parallel EGG system presented in this paper is based on a coarse-grained model of parallel processing and is implemented on a 16-node Linux PC cluster. The potential capability of parallel EGG system is demonstrated through the synthesis of a radix-4 signed-digit (SD) full adder circuit
Keywords :
adders; circuit CAD; evolutionary computation; graph theory; mathematics computing; multivalued logic circuits; optimisation; parallel algorithms; workstation clusters; 16-node Linux PC cluster; coarse-grained parallel processing model; graph-based evolutionary optimization technique; multiple-valued circuit synthesis; parallel evolutionary graph generation; radix-4 signed-digit full adder circuit; Logic;
Conference_Titel :
Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-1462-6
DOI :
10.1109/ISMVL.2002.1011076
