An error detection and correction scheme for RAMs with partial-write function

With the nano-scale VLSI technology and system-on-chip (SOC) design methodology, the reliability has become one major challenge in SOCs. Especially, embedded memory cores heavily impact on the reliability of SOCs. Error detection and correction (EDAC) techniques are well-known methodologies for detecting and correcting soft errors of random access memories. However, conventional EDAC techniques cannot effectively be applied to embedded memory cores with partial-write operation. This paper presents an EDAC scheme for embedded memory cores with partial-write operation. The area cost for implementing the proposed EDAC scheme in an 8K × 64-bit SRAM core with half-word parity (i.e., two parity bits for each word) is about 21% based on 0.18μm TSMC standard cells.