A high-precision time-to-digital converter using a two-level conversion scheme

This paper describes a design of time-to-digital converter (TDC) utilising a two-level conversion scheme. The first level is accomplished by a multi-phase sampling technique with the aid of delay-locked loop (DLL). Then the input signal and its adjacent sampling clock are manipulated and sent into a vernier delay line (VDL) sampling circuit. The proposed TDC can provide precise resolution with less hardware comparing to one level VDL sampling circuit possessing the same dynamic range. A new architecture of dual DLL circuit is also introduced to stabilize delay control against process and ambient variation. The test chip is designed and fabricated in 0.35μm digital process. With an input reference clock at 160MHz, the TDC achieves 24ps resolution. The DNL is less than ±0.55LSB and INL within +1LSB∼-1.5LSB.