Tunelling leakage current characterization of silicon oxide and high-k dielectics for advanced semiconductor devices

The continuum down-scaling lead the field-effect transistors in the nanometre region with devices and structures characterized by high doping drains/ sources and thin insulating layers. When the thickness of the layers attends 2 nm or less, the coupling between the semiconductor channel and the gate canpsilat be neglected. A correct quantum-mechanical model must correct evaluate the channel charge distribution and the leakage current flowing between the gate and the channel through tunnelling. The presented iterative approximation method for calculate the 1D device main electric parameters offer short time computation and was applied to study the thin silicon oxide and high-k dielectrics stacks combination for the silicon devices.