Title :
Optimization of multi-valued multi-level networks
Author :
Gao, M. ; Jiang, J.-H. ; Jiang, Y. ; Li, Y. ; Mishchenko, A. ; Sinha, S. ; Villa, T. ; Brayton, R.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
A program called MVSIS (Multi-Valued Sequential Interactive Synthesis) has been developed which optimizes multi-level multi-valued (MV) networks. We describe what such a network is and the capabilities contained in MVSIS. MVSIS is modeled after SIS (Sequential Interactive Synthesis), which synthesizes binary multi-level networks, but the logic network of MVSIS is such that all variables can be multi-valued, each with its own range. Included in MVSIS are almost all the technology-independent transformations of SIS for combinational and sequential logic synthesis as well as transformations specific to multi-valued nodes, such as "merge", "pair-decode" and "encode". MVSIS can read and write BLIF-MV and BLIF (Berkeley Logic Interchange Format) files which describe MV networks and binary networks respectively
Keywords :
circuit optimisation; high level synthesis; multivalued logic circuits; BLIF files; BLIF-MV files; Berkeley Logic Interchange Format; MVSIS program; Multi-Valued Sequential Interactive Synthesis; SIS; binary networks; combinational logic synthesis; encode transformation; merge transformation; multi-valued logic networks; multi-valued multi-level network optimization; multi-valued nodes; pair-decode transformation; sequential logic synthesis; technology-independent transformations; Application software; Circuit synthesis; Current mode circuits; Decoding; Delay; Hardware; Logic circuits; Logic devices; Multivalued logic; Network synthesis;
Conference_Titel :
Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-1462-6
DOI :
10.1109/ISMVL.2002.1011086
