DocumentCode :
1819936
Title :
Casta DIVA - a design for variability platform
Author :
Cotofana, Sorin ; Meenderinck, Cor
Author_Institution :
Comput. Eng. Lab., Delft Univ. of Technol., Delft
Volume :
2
fYear :
2008
fDate :
13-15 Oct. 2008
Firstpage :
373
Lastpage :
376
Abstract :
This paper introduces an architecture, Casta DIVA, which allows circuit and system designers to seamlessly incorporate design for variability in their designs to prevent large performance losses due to variations. The proposed architecture is generic as: (i) it takes into account all delay variation sources; (ii) applies solutions at design, test, and run time; (iii) and can be used as a template for all kind of systems, e.g., uni-processor, multi-processor. The Casta DIVA approach is introspective, that is, the system locally observes its own performance and adapts locally to the actual measured delay, by the use of local agents. To achieve global control too, the local agents are placed in a 3-level hierarchy. To reduce the extra hardware cost and to facilitate easy integration with existing design technologies we propose to utilize the JTAG boundary scan as test and communication infrastructure.
Keywords :
design for testability; fault tolerance; 3-level hierarchy; Casta DIVA; JTAG boundary scan; delay variation sources; design for variability platform; Circuit testing; Circuits and systems; Clocks; Communication system control; Computer architecture; Delay effects; Hardware; Logic; Performance loss; Temperature; computation platforms; delay variation; design for variability; design methodologies; fault tolerance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Conference, 2008. CAS 2008. International
Conference_Location :
Sinaia
ISSN :
1545-827X
Print_ISBN :
978-1-4244-2004-9
Type :
conf
DOI :
10.1109/SMICND.2008.4703430
Filename :
4703430
Link To Document :
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