• DocumentCode
    1820017
  • Title

    The word-level models for efficient computation of multiple-valued functions.2. LWL based model

  • Author

    Tomaszewska, Anna M. ; Yanushkevich, Svetlana N. ; Shmerko, Vlad P.

  • Author_Institution
    Fac. of Comput. Sci. & Inf. Syst., Tech. Univ. Szczecin, Poland
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    209
  • Lastpage
    215
  • Abstract
    For pt.1 see ibid., p. 202-8 (2002). This paper is a continuation of the study of neural-like networks (NLNs) for computation of multiple-valued logic (MVL) functions. NLN is defined as a feedforward network with no learning. In contrast to classical neural networks with threshold gates (TGs), the proposed NLN is built of so-called neuron-like gates (NLGs). It was shown in our previous study that NLG is modelled by a linear arithmetical expression (LAR). In this paper we show an even more simple NLG model. We have developed two word-level models; linear weighted logic expressions (LWLs) and a corresponding set of linear decision diagrams (LDDs). We compare the LWL- and LAR-based NLNs. The experimental study on large MVL circuits shows that the number of nodes in the LDDs derived from LWLs is four times less on average compared to those derived from LARs. They are also 2-7 times more compact (require less memory to store the terminal values)
  • Keywords
    Boolean functions; decision diagrams; feedforward neural nets; logic gates; multivalued logic; multivalued logic circuits; neural chips; Boolean functions; experimental study; feedforward neural network; linear arithmetical expression; linear decision diagrams; linear weighted logic expressions; memory; multiple-valued function computation; multiple-valued logic; neural-like networks; neuron-like gates; threshold gates; word-level models; Boolean functions; Computational modeling; Computer networks; Computer science; Delay; Information systems; Integrated circuit interconnections; Logic; Planarization; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on
  • Conference_Location
    Boston, MA
  • Print_ISBN
    0-7695-1462-6
  • Type

    conf

  • DOI
    10.1109/ISMVL.2002.1011091
  • Filename
    1011091