DocumentCode :
1820241
Title :
Multi-valued flip-flop with neuron-CMOS NMIN circuits
Author :
Inaba, Motoi ; Tanno, Koichi ; Ishizuka, Okihiko
Author_Institution :
Dept. of Inf. Sci. & Electron., Tsukuba Coll. of Technol., Japan
fYear :
2002
fDate :
2002
Firstpage :
282
Lastpage :
288
Abstract :
In this paper, the implementation and verification of the fundamental flip-flops for the voltage-mode multi-valued logic circuits on a conventional CMOS VLSI chip are presented. Using the quantized NMIN circuits and the analog NMIN circuits, two types of the multi-valued R-S flip-flop are designed like a wide-use R-S flip-flop with NAND circuits and are applied to the D flip-flop for multi-valued memory. In verification through HSPICE simulation, the proposed flip-flops perform with good results such as high noise margins and low power consumption
Keywords :
CMOS logic circuits; NAND circuits; SPICE; VLSI; flip-flops; formal verification; logic simulation; multivalued logic circuits; neural chips; CMOS VLSI chip; HSPICE simulation; NAND circuits; analog NMIN circuits; circuit verification; high noise margins; low power consumption; multi-valued flip-flop; multi-valued memory; neuron-CMOS NMIN circuits; quantized NMIN circuits; voltage-mode multi-valued logic circuits; Flip-flops; Logic circuits; Multivalued logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-1462-6
Type :
conf
DOI :
10.1109/ISMVL.2002.1011100
Filename :
1011100
Link To Document :
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