D0 muon readout electronics design

Volume

1

fYear

1996

fDate

2-9 Nov 1996

Firstpage

341

Abstract

The readout electronics designed for the D0 Muon Upgrade are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the D0 Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16-bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed

Keywords

analogue-digital conversion; calorimeters; detector circuits; digital readout; digital signal processing chips; high energy physics instrumentation computing; ionisation chambers; muon detection; nuclear electronics; position sensitive particle detectors; transition radiation detectors; trigger circuits; 16-bit fixed point DSP processor; D0 Muon Upgrade; D0 Trigger Framework; D0 muon readout electronics design; buffering; continuously running digitizers; data transfer; detector subsystems; frontends; readout hardware; serial links; system interface; timing signals; trigger system; Broadcasting; Computer buffers; Detectors; Digital signal processing; Electronic equipment testing; Hardware; Mesons; Process control; Readout electronics; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium, 1996. Conference Record., 1996 IEEE

Conference_Location

Anaheim, CA

ISSN

1082-3654

Print_ISBN

0-7803-3534-1

Type

conf

DOI

10.1109/NSSMIC.1996.590983

Filename

590983