DocumentCode :
1820388
Title :
PPS: a pipeline path-based scheduler
Author :
Rahmouni, Maher ; Jerraya, Ahmed A.
Author_Institution :
Lab. TIMA, Inst. Nat. Polytech. de Grenoble, France
fYear :
1995
fDate :
6-9 Mar 1995
Firstpage :
557
Lastpage :
561
Abstract :
This paper presents a scheduling algorithm that improves on other approaches when dealing with the synthesis of control-flow dominated behavioral descriptions. It achieves this through the use of a constraint-driven path-based scheduling algorithm. The suboptimality of the original path-based algorithms when dealing with loops is overcome through a new technique for pipelining different loop iterations during execution path generation. Results show that the algorithm always generates the fastest solution in terms of clock cycles
Keywords :
data flow graphs; hardware description languages; high level synthesis; iterative methods; scheduling; PPS; clock cycles; constraint-driven path-based scheduling; control-flow dominated behavioral descriptions; execution path generation; loop iterations; pipeline path-based scheduler; scheduling algorithm; Algorithm design and analysis; Circuit synthesis; Clocks; Compaction; Feedback loop; Flow graphs; Pipeline processing; Scheduling algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
Type :
conf
DOI :
10.1109/EDTC.1995.470345
Filename :
470345
Link To Document :
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