DocumentCode :
1820584
Title :
Yield-reliability modeling: experimental verification and application to burn-in reduction
Author :
Barnett, Thomas S. ; Singh, Adit D. ; Grady, Matt ; Purdy, Kathleen
Author_Institution :
Electr. & Comput. Eng., Auburn Univ., AL, USA
fYear :
2002
fDate :
2002
Firstpage :
75
Lastpage :
80
Abstract :
An integrated yield-reliability model is verified using burn-in data from 77,000 microprocessor units manufactured by IBM Microelectronics. The model is based on the fact that defects over semiconductor wafers are not randomly distributed, but have a tendency to cluster. It is shown that this fact can be exploited to produce die of varying reliability by sorting die into bins based on how many of their neighbors test faulty. Die that test good at wafer probe, yet come from regions with many faulty die, have a higher incidence of infant mortality failure than die from regions with few faulty die. The yield-reliability model is used to predict the fraction of good die in each bin following wafer probing as well as the fraction of failures in each bin following stress testing (e.g. burn-in). Results show excellent agreement between model predictions and observed data.
Keywords :
failure analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; parameter estimation; probability; production testing; IBM Microelectronics; burn-in data; defect clustering; die reliability; die sorting; failures; infant mortality failure; integrated yield-reliability model; microprocessor units; model predictions; semiconductor wafer defects; stress testing; wafer probing; Microelectronics; Microprocessors; Predictive models; Probes; Semiconductor device manufacture; Semiconductor device modeling; Sorting; Stress; Testing; Virtual manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
Type :
conf
DOI :
10.1109/VTS.2002.1011114
Filename :
1011114
Link To Document :
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