Design of an interconnect topology for multi-cores and scale-out workloads

Scale-out workloads are applications that are typically executed in a cloud environment and exhibit high level of request level parallelism. Such workloads benefit from processor organizations with very high core count since multiple requests can be serviced simultaneously by threads running on these cores. The characteristics of these workloads indicate that they have high instruction footprints exceeding the capacities of private caches, operate on large datasets with limited reuse and have minimal coherence activity due to lesser data sharing. The characteristics also indicate that the active instruction window can be captured by a Last Level Cache (LLC) size of 8MB. New processor organizations have been discussed in literature that tailors the interconnection among cores to match the communication pattern arising out of the characteristics of scale-out workloads. The focus of the current work is to take the approach of separating a core and LLC bank from a single tile as specified in literature and design a different interconnection topology for cores and LLC banks to reduce the latency of accessing the LLC to improve performance. In the current work, four cores and a LLC bank are designed to connect to a router forming a star topology and the routers (>4) are designed to form a 2D flattened butterfly topology. The current design has been targeted at 8 cores and has been implemented using the Bluespec System Verilog HDL (Hardware Description Language) and the design has been synthesized using Xilinx Vivado 2013.2 targeting Zynq^®-7000 product family of FPGA boards. The design has been evaluated for different amounts of offered traffic and the average latency and the throughput of the interconnection network for uniform random traffic pattern has been calculated. An injection rate of 0.05packets/cycle/core which corresponds to the maximum L2 miss rate for scale-out workloads gives an average packet latency of 29.5 clock cycles and a through- ut of 0.52packets/cycle.