DocumentCode :
1820625
Title :
An efficient method for computing exact path delay fault coverage
Author :
Kapoor, Bhanu
Author_Institution :
Integrated Syst. Labs., Texas Instrum. Inc., Dallas, TX, USA
fYear :
1995
fDate :
6-9 Mar 1995
Firstpage :
516
Lastpage :
520
Abstract :
We describe algorithms and data structures for accurate and efficient computation of path delay fault coverage. Our method uses an interval-based representation of consecutively numbered path delay faults. We describe a modified 2-3 tree data structure to store and manipulate these intervals to keep track of tested faults. Some results obtained using non-robust simulation of benchmark circuits suggest the viability of this approach
Keywords :
automatic test software; circuit analysis computing; delays; fault diagnosis; logic testing; tree data structures; algorithms; data structures; interval-based representation; modified 2-3 tree data structure; path delay fault coverage; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Data structures; Delay effects; Delay estimation; Polynomials; Tree data structures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
Type :
conf
DOI :
10.1109/EDTC.1995.470352
Filename :
470352
Link To Document :
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