DocumentCode :
1820822
Title :
A W-band stacked FET power amplifier with 17 dBm Psat in 45-nm SOI CMOS
Author :
Jayamon, J. ; Agah, A. ; Hanafi, B. ; Dabag, H. ; Buckwalter, J. ; Asbeck, P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, La Jolla, CA, USA
fYear :
2013
fDate :
20-20 Jan. 2013
Firstpage :
85
Lastpage :
87
Abstract :
A 90GHz power amplifier implemented with three series-connected (stacked) FETs in 45-nm SOI CMOS is reported. Stacking FETs allows increasing voltage handling capability of circuits with highly scaled CMOS transistors. This work shows for the first time that the stacking strategy is effective up to W band. The amplifier achieves power gain of 8 dB at 91 GHz with 3 dB bandwidth of 18 GHz using a supply voltage of 4.2 V. It delivers saturated output power of 17.3 dBm in 88-90 GHz range with peak PAE of 9 %. The PA chip occupies 0.256 mm2 including the pads. This chip demonstrates the highest output power from a CMOS PA in this frequency regime.
Keywords :
CMOS integrated circuits; MOSFET; millimetre wave amplifiers; millimetre wave integrated circuits; silicon-on-insulator; PA chip; PAE; SOI CMOS; W-band stacked FET power amplifier; bandwidth 18 GHz; efficiency 9 percent; frequency 88 GHz to 90 GHz; frequency regime; gain 8 dB; highly scaled CMOS transistors; series-connected FET; size 45 nm; voltage 4.2 V; voltage handling capability; CMOS integrated circuits; Field effect transistors; Gain; Logic gates; Power amplifiers; Power generation; Stacking; CMOS SOI; Power amplifier; W-band; millimeter-wave; stacked FET;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Amplifiers for Wireless and Radio Applications (PAWR), 2013 IEEE Topical Conference on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-2915-6
Electronic_ISBN :
978-1-4673-2931-6
Type :
conf
DOI :
10.1109/PAWR.2013.6490197
Filename :
6490197
Link To Document :
بازگشت