DocumentCode
1820866
Title
Testing high-speed SoCs using low-speed ATEs
Author
Nourani, Mehrdad ; Chin, James
Author_Institution
Center for Intergrated Circuits & Syst., Univ. of Texas at Dallas, Richardson, TX, USA
fYear
2002
fDate
2002
Firstpage
133
Lastpage
138
Abstract
Presents a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate sending the test patterns and collecting the signatures. An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.
Keywords
application specific integrated circuits; automatic test equipment; high-speed integrated circuits; integer programming; integrated circuit testing; linear programming; logic testing; ILP formulation; coordinate sending; hardware cost; high-speed SoCs; interface circuit; low-speed ATEs; overall test time; test data; test methodology; test patterns; Application specific integrated circuits; Built-in self-test; Circuit testing; Circuits and systems; Clocks; Costs; Delay; Frequency; Hardware; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN
0-7695-1570-3
Type
conf
DOI
10.1109/VTS.2002.1011124
Filename
1011124
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