Title :
Prediction of interconnect delay in logic synthesis
Author :
Jyu, Henry H F ; Malik, Sharad
Author_Institution :
EPIC Desing Technol. Inc., Santa Clara, CA, USA
Abstract :
IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design-primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model is proposed to predict the average wire length for each net in a given gate-level netlist and a particular layout tool
Keywords :
delays; estimation theory; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated logic circuits; logic design; piecewise-linear techniques; IC design; average wire length; estimation model; gate-level netlist; interconnect delay prediction; interconnection wires; layout tool; logic design; logic synthesis; Delay effects; Delay estimation; Digital systems; Integrated circuit interconnections; Logic circuits; Logic design; Predictive models; Routing; Wires; Wiring;
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
DOI :
10.1109/EDTC.1995.470363
