Analyzing the performance and energy impact of 3D memory integration on embedded DSPs

Recently, three-dimensional integration technology has allowed researchers and designers to explore novel architectures for computing systems. Due to the memory-intensive nature of signal processing systems, DSPs can greatly benefit from 3D memory integration technology realized by vertically stacking high-density memory below processing cores. In this paper, we analyze the energy and performance impacts of 3D memory integration in DSP systems by exploring a wide variety of memory configurations the technology enables. Our analysis demonstrates that a 3D memory hierarchy can increase performance by an average of 20.6% while decreasing energy by 6.7% when compared to our baseline 2D memory hierarchy, with a processor similar to a Texas Instrument C67× DSP. This proposed memory architecture also allows us to scale the voltage and frequency to decrease energy consumption by an average of 23% without decreasing performance.