Area versus detection latency trade-offs in self-checking memory design

With the increasing need for on-line reliability today´s electronic systems often require certain levels of self-checking. Depending on its application, the level of self-checking, i.e. the detection latency, of a given system is determined. Most of the known on-line testing schemes provide a fixed level of self-checking, hence do not allow flexibility in meeting the allowed detection latency and hardware overhead. This paper presents a new self-checking scheme for memories (RAMs, ROMs, etc.), which provides trade-off between hardware cost versus detection latency. The scheme takes the required detection latency and determines the codes to meet the system requirements. The paper also illustrates the flexibility of this scheme with certain implementation examples