DocumentCode
1821160
Title
Compiler Optimization to Reduce Cache Power with Victim Cache
Author
Cheng-Yu Lee ; Jen-Chieh Chang ; Rong-Guey Chang
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
fYear
2012
fDate
4-7 Sept. 2012
Firstpage
841
Lastpage
844
Abstract
Victim cache can buffer blocks discarded from the cache on a miss before going to the next lower-level memory to improve performance. Compared with the previous work, rather than only improve performance, we design a modified victim cache to reduce power consumption by minimizing accesses to L2 cache, miss rate, and miss penalty in this paper. With the help of this new victim cache, we can turn on/off cache block in a software way to save power and improve performance. The proposed approach can analyze an application, perform scheduling, and then insert the instrumention instructions in the code to control victim cache. The results shows that the proposed approach can improve performance about 6.5%, reduce 32.66% of cache miss, and save 4.19% of power consumption with 2k direct-mapped cache at the cost only of 1.9% code expansion on average.
Keywords
cache storage; optimisation; program compilers; L2 cache; cache power; compiler optimization; miss penalty; miss rate; modified victim cache; next lower-level memory; Computer architecture; Hardware; IEEE Computer Society; Optimization; Power demand; Software; USA Councils; cache; compiler; low-power; optimization; victim cache;
fLanguage
English
Publisher
ieee
Conference_Titel
Ubiquitous Intelligence & Computing and 9th International Conference on Autonomic & Trusted Computing (UIC/ATC), 2012 9th International Conference on
Conference_Location
Fukuoka
Print_ISBN
978-1-4673-3084-8
Type
conf
DOI
10.1109/UIC-ATC.2012.36
Filename
6331990
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