ASIC design for communications satellite payloads

With the recent feature size reductions and the improvements in radiation hardness of CMOS technology it is becoming attractive to include multi-ASIC DSP processors within the payload of communications satellites. Key constraints specific to satellites are low mass and power overheads, parameters that are minimised using advanced signal processing algorithms and top down design techniques. This paper describes the ASIC design methodology adopted at British Aerospace Space Systems. This maintains the advantages of proven in-house algorithm development software to specify the system requirements. This is complemented by an in-house power and mass estimation tool which determines a partitioning strategy of functions to ASICs. A VHDL description is developed and tested against the algorithmic specification by selecting functions from a library of tested generic VHDL models. ASIC specifications and detailed ASIC designs are generated with the aid of the results of the power and mass estimation tool. The output is a VHDL model suitable for logic synthesis